Matches in LOV for { ?s <http://www.w3.org/2000/01/rdf-schema#label> ?o. }
- B.1.4.4 label "B.1.4.4. Verification".
- B.1.5.0 label "B.1.5.0. Direct data manipulation".
- B.1.5.1 label "B.1.5.1. Firmware support of operating systems/instruction sets".
- B.1.5.2 label "B.1.5.2. Instruction set interpretation".
- B.1.5.3 label "B.1.5.3. Peripheral control".
- B.1.5.4 label "B.1.5.4. Special-purpose".
- B.1.m label "B.1.m. Miscellaneous".
- B.2.0 label "B.2.0. General".
- B.2.1.0 label "B.2.1.0. Calculator".
- B.2.1.1 label "B.2.1.1. Parallel".
- B.2.1.2 label "B.2.1.2. Pipeline".
- B.2.2.0 label "B.2.2.0. Simulation".
- B.2.2.1 label "B.2.2.1. Verification".
- B.2.2.2 label "B.2.2.2. Worst-case analysis".
- B.2.3.0 label "B.2.3.0. Diagnostics".
- B.2.3.1 label "B.2.3.1. Error-checking".
- B.2.3.2 label "B.2.3.2. Redundant design".
- B.2.3.3 label "B.2.3.3. Test generation".
- B.2.4.0 label "B.2.4.0. Algorithms".
- B.2.4.1 label "B.2.4.1. Cost/performance".
- B.2.m label "B.2.m. Miscellaneous".
- B.3.0 label "B.3.0. General".
- B.3.1.0 label "B.3.1.0. Dynamic memory".
- B.3.1.1 label "B.3.1.1. Read-only memory".
- B.3.1.2 label "B.3.1.2. Static memory".
- B.3.2.0 label "B.3.2.0. Associative memories".
- B.3.2.1 label "B.3.2.1. Cache memories".
- B.3.2.2 label "B.3.2.2. Interleaved memories".
- B.3.2.3 label "B.3.2.3. Mass storage".
- B.3.2.4 label "B.3.2.4. Primary memory".
- B.3.2.5 label "B.3.2.5. Sequential-access memory".
- B.3.2.6 label "B.3.2.6. Shared memory".
- B.3.2.7 label "B.3.2.7. Virtual memory".
- B.3.3.0 label "B.3.3.0. Formal models".
- B.3.3.1 label "B.3.3.1. Simulation".
- B.3.3.2 label "B.3.3.2. Worst-case analysis".
- B.3.4.0 label "B.3.4.0. Diagnostics".
- B.3.4.1 label "B.3.4.1. Error-checking".
- B.3.4.2 label "B.3.4.2. Redundant design".
- B.3.4.3 label "B.3.4.3. Test generation".
- B.3.m label "B.3.m. Miscellaneous".
- B.4.0 label "B.4.0. General".
- B.4.1.0 label "B.4.1.0. Processors".
- B.4.1.1 label "B.4.1.1. Receivers".
- B.4.1.2 label "B.4.1.2. Transmitters".
- B.4.2.0 label "B.4.2.0. Channels and controllers".
- B.4.2.1 label "B.4.2.1. Data terminals and printers".
- B.4.2.2 label "B.4.2.2. Image display".
- B.4.2.3 label "B.4.2.3. Voice".
- B.4.3.0 label "B.4.3.0. Asynchronous/synchronous operation".
- B.4.3.1 label "B.4.3.1. Fiber optics".
- B.4.3.2 label "B.4.3.2. Interfaces".
- B.4.3.3 label "B.4.3.3. Parallel I/O".
- B.4.3.4 label "B.4.3.4. Physical structures".
- B.4.3.5 label "B.4.3.5. Topology".
- B.4.4.0 label "B.4.4.0. Formal models".
- B.4.4.1 label "B.4.4.1. Simulation".
- B.4.4.2 label "B.4.4.2. Verification".
- B.4.4.3 label "B.4.4.3. Worst-case analysis".
- B.4.5.0 label "B.4.5.0. Built-in tests".
- B.4.5.1 label "B.4.5.1. Diagnostics".
- B.4.5.2 label "B.4.5.2. Error-checking".
- B.4.5.3 label "B.4.5.3. Hardware reliability".
- B.4.5.4 label "B.4.5.4. Redundant design".
- B.4.5.5 label "B.4.5.5. Test generation".
- B.4.m label "B.4.m. Miscellaneous".
- B.5.0 label "B.5.0. General".
- B.5.1.0 label "B.5.1.0. Arithmetic and logic units".
- B.5.1.1 label "B.5.1.1. Control design".
- B.5.1.2 label "B.5.1.2. Data-path design".
- B.5.1.3 label "B.5.1.3. Memory design".
- B.5.1.4 label "B.5.1.4. Styles".
- B.5.2.0 label "B.5.2.0. Automatic synthesis".
- B.5.2.1 label "B.5.2.1. Hardware description languages".
- B.5.2.2 label "B.5.2.2. Optimization".
- B.5.2.3 label "B.5.2.3. Simulation".
- B.5.2.4 label "B.5.2.4. Verification".
- B.5.3.0 label "B.5.3.0. Built-in tests".
- B.5.3.1 label "B.5.3.1. Error-checking".
- B.5.3.2 label "B.5.3.2. Redundant design".
- B.5.3.3 label "B.5.3.3. Test generation".
- B.5.3.4 label "B.5.3.4. Testability".
- B.5.m label "B.5.m. Miscellaneous".
- B.6.0 label "B.6.0. General".
- B.6.1.0 label "B.6.1.0. Cellular arrays and automata".
- B.6.1.1 label "B.6.1.1. Combinational logic".
- B.6.1.2 label "B.6.1.2. Logic arrays".
- B.6.1.3 label "B.6.1.3. Memory control and access".
- B.6.1.4 label "B.6.1.4. Memory used as logic".
- B.6.1.5 label "B.6.1.5. Parallel circuits".
- B.6.1.6 label "B.6.1.6. Sequential circuits".
- B.6.2.0 label "B.6.2.0. Built-in tests".
- B.6.2.1 label "B.6.2.1. Error-checking".
- B.6.2.2 label "B.6.2.2. Redundant design".
- B.6.2.3 label "B.6.2.3. Test generation".
- B.6.2.4 label "B.6.2.4. Testability".
- B.6.3.0 label "B.6.3.0. Automatic synthesis".
- B.6.3.1 label "B.6.3.1. Hardware description languages".
- B.6.3.2 label "B.6.3.2. Optimization".
- B.6.3.3 label "B.6.3.3. Simulation".