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- Delay_Insensitive_Minterm_Synthesis abstract "Invented by David E. Muller, the DIMS (Delay Insensitive Minterm Synthesis) system is an asynchronous design methodology making the least possible timing assumptions. Assuming only the Quasi-Delay-Insensitive delay model the generated designs need little if any timing hazard testing. The basis for DIMS is the use of two wires to represent each bit of data. This is known as a Dual-Rail data encoding. Parts of the system communicate using the early four-phase asynchronous protocol.The construction of DIMS logic gates comprises generating every possible minterm using a row of C-elements and then gathering the outputs of these using OR gates which generate the true and false output signals. With two dual-rail inputs the gate would be composed of four two-input C-elements. A three input gate uses eight three-input C-elements.File:Dims gate.pngLatches are constructed using two C-elements to store the data and an OR gate to acknowledge the input once the data has been latched by attaching as its inputs the data output wires. The acknowledge from the forward stage is inverted and passed to the C-elements to allow them to reset once the computation has completed. This latch design is known as the 'half latch'. Other asynchronous latches provide a higher data capacity and levels of decoupling.File:Dims latch.pngDIMS designs are large and slow but they have the advantage of being very robust.".
- Delay_Insensitive_Minterm_Synthesis thumbnail Dims_gate.png?width=300.
- Delay_Insensitive_Minterm_Synthesis wikiPageID "2156176".
- Delay_Insensitive_Minterm_Synthesis wikiPageRevisionID "490968895".
- Delay_Insensitive_Minterm_Synthesis hasPhotoCollection Delay_Insensitive_Minterm_Synthesis.
- Delay_Insensitive_Minterm_Synthesis subject Category:Digital_electronics.
- Delay_Insensitive_Minterm_Synthesis comment "Invented by David E. Muller, the DIMS (Delay Insensitive Minterm Synthesis) system is an asynchronous design methodology making the least possible timing assumptions. Assuming only the Quasi-Delay-Insensitive delay model the generated designs need little if any timing hazard testing. The basis for DIMS is the use of two wires to represent each bit of data. This is known as a Dual-Rail data encoding.".
- Delay_Insensitive_Minterm_Synthesis label "Delay Insensitive Minterm Synthesis".
- Delay_Insensitive_Minterm_Synthesis sameAs m.06qzp3.
- Delay_Insensitive_Minterm_Synthesis sameAs Q5253469.
- Delay_Insensitive_Minterm_Synthesis sameAs Q5253469.
- Delay_Insensitive_Minterm_Synthesis wasDerivedFrom Delay_Insensitive_Minterm_Synthesis?oldid=490968895.
- Delay_Insensitive_Minterm_Synthesis depiction Dims_gate.png.
- Delay_Insensitive_Minterm_Synthesis isPrimaryTopicOf Delay_Insensitive_Minterm_Synthesis.