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- OpenRISC abstract "OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support.A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL). A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups demonstrated ORPSoC and other OR1200 based designs running on FPGA.".
- OpenRISC wikiPageExternalLink 25HarvJLTech131.pdf.
- OpenRISC wikiPageExternalLink LLVM.
- OpenRISC wikiPageExternalLink Main_Page.
- OpenRISC wikiPageExternalLink toolchain-build.html.
- OpenRISC wikiPageExternalLink www.beyondsemi.com.
- OpenRISC wikiPageExternalLink www.dynalith.com.
- OpenRISC wikiPageExternalLink OEG20000228S0007.
- OpenRISC wikiPageExternalLink default.aspx.
- OpenRISC wikiPageExternalLink www.imperas.com.
- OpenRISC wikiPageExternalLink www.jennic.com.
- OpenRISC wikiPageExternalLink ?id=wallentowitz.
- OpenRISC wikiPageExternalLink www.opencores.org.
- OpenRISC wikiPageExternalLink www.orsoc.se.
- OpenRISC wikiPageExternalLink openrisc-1200-soft-processor.
- OpenRISC wikiPageExternalLink wiki.
- OpenRISC wikiPageID "411760".
- OpenRISC wikiPageRevisionID "604713889".
- OpenRISC bits "32".
- OpenRISC design "RISC".
- OpenRISC designer "OpenCores community".
- OpenRISC encoding "Fixed".
- OpenRISC fpr "Optional".
- OpenRISC gpr "16".
- OpenRISC hasPhotoCollection OpenRISC.
- OpenRISC name "OpenRISC".
- OpenRISC open "Yes".
- OpenRISC subject Category:Embedded_microprocessors.
- OpenRISC subject Category:Open_microprocessors.
- OpenRISC type Artifact100021939.
- OpenRISC type Chip103020034.
- OpenRISC type Conductor103088707.
- OpenRISC type Device103183080.
- OpenRISC type EmbeddedMicroprocessors.
- OpenRISC type Instrumentality103575240.
- OpenRISC type Microprocessor103760310.
- OpenRISC type Object100002684.
- OpenRISC type OpenMicroprocessors.
- OpenRISC type PhysicalEntity100001930.
- OpenRISC type SemiconductorDevice104171831.
- OpenRISC type Whole100003553.
- OpenRISC comment "OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support.A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language.".
- OpenRISC label "OpenRISC".
- OpenRISC label "OpenRISC".
- OpenRISC label "OpenRISC".
- OpenRISC label "OpenRISC".
- OpenRISC label "OpenRISC".
- OpenRISC label "OpenRISC".
- OpenRISC label "OpenRISC".
- OpenRISC sameAs OpenRISC.
- OpenRISC sameAs OpenRISC.
- OpenRISC sameAs OpenRISC.
- OpenRISC sameAs OpenRISC.
- OpenRISC sameAs OpenRISC.
- OpenRISC sameAs m.02559x.
- OpenRISC sameAs Q1092481.
- OpenRISC sameAs Q1092481.
- OpenRISC sameAs OpenRISC.
- OpenRISC wasDerivedFrom OpenRISC?oldid=604713889.
- OpenRISC isPrimaryTopicOf OpenRISC.