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- XOP_instruction_set abstract "The XOP (eXtended Operations) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011.The XOP instruction set contains several different types of vector instructions since it was originally intended as a major upgrade to SSE. Most of the instructions are integer instructions, but it also contains floating point permutation and floating point fraction extraction instructions. See the index for a list of instruction types.".
- XOP_instruction_set wikiPageID "22701763".
- XOP_instruction_set wikiPageRevisionID "606810997".
- XOP_instruction_set hasPhotoCollection XOP_instruction_set.
- XOP_instruction_set subject Category:Advanced_Micro_Devices.
- XOP_instruction_set subject Category:SIMD_computing.
- XOP_instruction_set subject Category:X86_instructions.
- XOP_instruction_set type AdvancedMicroDevices.
- XOP_instruction_set type Artifact100021939.
- XOP_instruction_set type Device103183080.
- XOP_instruction_set type Instrumentality103575240.
- XOP_instruction_set type Object100002684.
- XOP_instruction_set type PhysicalEntity100001930.
- XOP_instruction_set type Whole100003553.
- XOP_instruction_set comment "The XOP (eXtended Operations) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011.The XOP instruction set contains several different types of vector instructions since it was originally intended as a major upgrade to SSE.".
- XOP_instruction_set label "XOP instruction set".
- XOP_instruction_set sameAs m.05zqd3g.
- XOP_instruction_set sameAs Q8042372.
- XOP_instruction_set sameAs Q8042372.
- XOP_instruction_set sameAs XOP_instruction_set.
- XOP_instruction_set wasDerivedFrom XOP_instruction_set?oldid=606810997.
- XOP_instruction_set isPrimaryTopicOf XOP_instruction_set.