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- DLX abstract "The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.There are two known implementations: ASPIDA and VAMP. ASPIDA project resulted in a core with many nice features: open source, supports Wishbone, asynchronous design, supports multiple ISA's, ASIC proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with PVS, implemented in Verilog, and runs on a Xilinx FPGA. A full stack from compiler to kernel to TCP/IP was built on it.".
- DLX wikiPageExternalLink download;jsessionid=F3092E4572A237F069257DFF168CB07A?doi=10.1.1.217.2251&rep=rep1&type=pdf.
- DLX wikiPageExternalLink HERA.
- DLX wikiPageExternalLink windlx.html.
- DLX wikiPageExternalLink project,aspida.
- DLX wikiPageExternalLink opendlx.
- DLX wikiPageExternalLink escape.
- DLX wikiPageExternalLink dlx.html.
- DLX wikiPageExternalLink dlx.php.
- DLX wikiPageExternalLink instructions.pdf.
- DLX wikiPageID "482305".
- DLX wikiPageRevisionID "601925780".
- DLX bits "32".
- DLX branching "Condition register".
- DLX design "RISC".
- DLX designer "John L. Hennessy and David A. Patterson".
- DLX encoding "Fixed".
- DLX endianness Endianness.
- DLX extensions "None, but MDMX & MIPS-3D could be used".
- DLX fpr "32".
- DLX gpr "31".
- DLX hasPhotoCollection DLX.
- DLX introduced "1990.0".
- DLX name "DLX".
- DLX open "Yes".
- DLX type store_architecture.
- DLX type Register-Register.
- DLX version "1".
- DLX subject Category:Educational_abstract_machines.
- DLX subject Category:Instruction_set_architectures.
- DLX type Architecture102734725.
- DLX type Artifact100021939.
- DLX type Building102913152.
- DLX type InstructionSetArchitectures.
- DLX type Object100002684.
- DLX type PhysicalEntity100001930.
- DLX type Structure104341686.
- DLX type Whole100003553.
- DLX type YagoGeoEntity.
- DLX type YagoPermanentlyLocatedEntity.
- DLX comment "The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS CPU.".
- DLX label "DLX (informatica)".
- DLX label "DLX".
- DLX label "DLX".
- DLX label "DLX".
- DLX label "DLX".
- DLX label "DLX".
- DLX label "DLX".
- DLX label "DLX-Prozessor".
- DLX sameAs DLX-Prozessor.
- DLX sameAs DLX.
- DLX sameAs DLX.
- DLX sameAs DLX_(informatica).
- DLX sameAs DLX.
- DLX sameAs DLX.
- DLX sameAs m.02ftdf.
- DLX sameAs Q362451.
- DLX sameAs Q362451.
- DLX sameAs DLX.
- DLX wasDerivedFrom DLX?oldid=601925780.
- DLX isPrimaryTopicOf DLX.