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- aggregation classification "A1".
- aggregation creator person.
- aggregation creator person.
- aggregation creator person.
- aggregation creator person.
- aggregation creator person.
- aggregation date "2014".
- aggregation format "application/pdf".
- aggregation hasFormat 4095955.bibtex.
- aggregation hasFormat 4095955.csv.
- aggregation hasFormat 4095955.dc.
- aggregation hasFormat 4095955.didl.
- aggregation hasFormat 4095955.doc.
- aggregation hasFormat 4095955.json.
- aggregation hasFormat 4095955.mets.
- aggregation hasFormat 4095955.mods.
- aggregation hasFormat 4095955.rdf.
- aggregation hasFormat 4095955.ris.
- aggregation hasFormat 4095955.txt.
- aggregation hasFormat 4095955.xls.
- aggregation hasFormat 4095955.yaml.
- aggregation isPartOf urn:issn:2156-3950.
- aggregation language "eng".
- aggregation rights "I have transferred the copyright for this publication to the publisher".
- aggregation subject "Technology and Engineering".
- aggregation title "High yield fabrication process for 3D-stacked ultra-thin chip packages using photo-definable polyimide and symmetry in packages".
- aggregation abstract "Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. At first thinned dies are embedded in a polyimide interposer with a fine-pitch metal fan-out resulting Ultra-Thin Chip Packages (UTCP), next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by introduction of an additional layer of interposer which makes it flat at the chip edge and thus the whole packages is named as “Flat-UTCP”. In addition to that, randomness in non-functional package positions per panel reduces the overall yield of the whole process up to certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of 4 EEPROM dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield.".
- aggregation authorList BK996217.
- aggregation endPage "167".
- aggregation issue "1".
- aggregation startPage "158".
- aggregation volume "4".
- aggregation aggregates 4252101.
- aggregation aggregates 4252109.
- aggregation isDescribedBy 4095955.
- aggregation similarTo TCPMT.2013.2284068.
- aggregation similarTo LU-4095955.