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- aggregation classification "P1".
- aggregation creator person.
- aggregation creator person.
- aggregation date "2007".
- aggregation format "application/pdf".
- aggregation hasFormat 750978.bibtex.
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- aggregation isPartOf urn:isbn:978-1-4244-1257-0.
- aggregation isPartOf urn:issn:1063-6404.
- aggregation language "eng".
- aggregation publisher "IEEE".
- aggregation title "Statistical Simulation of Chip Multiprocessors Running Multi-Program Workloads".
- aggregation abstract "This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to measure a number of important program execution characteristics, generate a synthetic trace, and simulate that synthetic trace. The important benefit is that a synthetic trace is very small compared to real program traces. This paper advances statistical simulation by modeling shared resources, such as shared caches and off-chip bandwidth. This is done (i) by collecting cache set access probabilities and per-set LRU stack depth profiles, and (ii) by modeling a program's time-varying execution behavior in the synthetic trace. The key benefit is that the statistical profile is independent of a given cache configuration and the amount of multiprocessing, which enables statistical simulation to model conflict behavior in shared caches when multiple programs are co-executing on a CMP. We demonstrate that statistical simulation is both accurate and fast with average IPC prediction errors of less than 5.5% and simulation speedups of 40X to 70X compared to the detailed simulation of 100M-instruction traces. This makes statistical simulation a viable tool for CMP design space exploration.".
- aggregation authorList BK80248.
- aggregation endPage "471".
- aggregation startPage "464".
- aggregation aggregates 831854.
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