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- Field_Programmable_Nanowire_Interconnect abstract "Field Programmable Nanowire Interconnect (often abbreviated FPNI) is a new computer architecture developed by Hewlett-Packard. This is a defect-tolerant architecture, using the results of the Teramac experiment.Details: The design combines a nanoscale crossbar switch structure with conventional CMOS to create a hybrid chip that is simpler to fabricate and offers greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit -- while providing up to eight times the density at less cost. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's Law without having to shrink the transistors.".
- Field_Programmable_Nanowire_Interconnect wikiPageExternalLink 035204.
- Field_Programmable_Nanowire_Interconnect wikiPageID "10069959".
- Field_Programmable_Nanowire_Interconnect wikiPageRevisionID "545419638".
- Field_Programmable_Nanowire_Interconnect hasPhotoCollection Field_Programmable_Nanowire_Interconnect.
- Field_Programmable_Nanowire_Interconnect subject Category:Gate_arrays.
- Field_Programmable_Nanowire_Interconnect type Abstraction100002137.
- Field_Programmable_Nanowire_Interconnect type Arrangement107938773.
- Field_Programmable_Nanowire_Interconnect type Array107939382.
- Field_Programmable_Nanowire_Interconnect type GateArrays.
- Field_Programmable_Nanowire_Interconnect type Group100031264.
- Field_Programmable_Nanowire_Interconnect comment "Field Programmable Nanowire Interconnect (often abbreviated FPNI) is a new computer architecture developed by Hewlett-Packard. This is a defect-tolerant architecture, using the results of the Teramac experiment.Details: The design combines a nanoscale crossbar switch structure with conventional CMOS to create a hybrid chip that is simpler to fabricate and offers greater flexibility in the choice of nanoscale devices.".
- Field_Programmable_Nanowire_Interconnect label "Field Programmable Nanowire Interconnect".
- Field_Programmable_Nanowire_Interconnect sameAs m.02q0t4x.
- Field_Programmable_Nanowire_Interconnect sameAs Q5446940.
- Field_Programmable_Nanowire_Interconnect sameAs Q5446940.
- Field_Programmable_Nanowire_Interconnect sameAs Field_Programmable_Nanowire_Interconnect.
- Field_Programmable_Nanowire_Interconnect wasDerivedFrom Field_Programmable_Nanowire_Interconnect?oldid=545419638.
- Field_Programmable_Nanowire_Interconnect isPrimaryTopicOf Field_Programmable_Nanowire_Interconnect.