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- High-level_synthesis abstract "High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages., although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC. The code is analyzed, architecturally constrained, and scheduled to create a register-transfer level (RTL) hardware design language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation. Verification of the RTL is an important part of the process.Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level.While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and Ansi C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.".
- High-level_synthesis wikiPageExternalLink soc.
- High-level_synthesis wikiPageExternalLink esl.
- High-level_synthesis wikiPageExternalLink www-gaut.
- High-level_synthesis wikiPageExternalLink legup.eecg.utoronto.ca.
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- High-level_synthesis wikiPageExternalLink www.c-to-verilog.com.
- High-level_synthesis wikiPageExternalLink www.cebatech.com.
- High-level_synthesis wikiPageExternalLink www.chipvision.com.
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- High-level_synthesis wikiPageExternalLink 0480.html.
- High-level_synthesis wikiPageExternalLink hercules.
- High-level_synthesis wikiPageExternalLink www.vsyn.ru.
- High-level_synthesis wikiPageExternalLink index.htm.
- High-level_synthesis wikiPageExternalLink www.yxi.com.
- High-level_synthesis wikiPageExternalLink Shang.
- High-level_synthesis wikiPageID "19878629".
- High-level_synthesis wikiPageRevisionID "603371401".
- High-level_synthesis hasPhotoCollection High-level_synthesis.
- High-level_synthesis subject Category:Electronic_design_automation.
- High-level_synthesis comment "High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing.".
- High-level_synthesis label "High-level synthesis".
- High-level_synthesis label "高级综合".
- High-level_synthesis sameAs m.04q8ygk.
- High-level_synthesis sameAs Q5754574.
- High-level_synthesis sameAs Q5754574.
- High-level_synthesis wasDerivedFrom High-level_synthesis?oldid=603371401.
- High-level_synthesis isPrimaryTopicOf High-level_synthesis.