Matches in DBpedia 2014 for { <http://dbpedia.org/resource/OpenRISC_1200> ?p ?o. }
Showing items 1 to 23 of
23
with 100 items per page.
- OpenRISC_1200 abstract "The OpenRISC 1200 (OR1200) is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture [1]. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".
- OpenRISC_1200 thumbnail OR1200.png?width=300.
- OpenRISC_1200 wikiPageExternalLink openrisc1200_spec.pdf.
- OpenRISC_1200 wikiPageExternalLink openrisc,architecture.
- OpenRISC_1200 wikiPageExternalLink Implementation_information.
- OpenRISC_1200 wikiPageExternalLink UClibc_tool_chain_test_results.
- OpenRISC_1200 wikiPageExternalLink openrisc.html.
- OpenRISC_1200 wikiPageExternalLink Free-32-bit-processor-core-hits-the-Net.
- OpenRISC_1200 wikiPageExternalLink openrisc,or1200.
- OpenRISC_1200 wikiPageExternalLink ?s=devkit.
- OpenRISC_1200 wikiPageID "16732958".
- OpenRISC_1200 wikiPageRevisionID "552963844".
- OpenRISC_1200 hasPhotoCollection OpenRISC_1200.
- OpenRISC_1200 subject Category:Open_microprocessors.
- OpenRISC_1200 subject Category:Soft_microprocessors.
- OpenRISC_1200 comment "The OpenRISC 1200 (OR1200) is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture [1]. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).".
- OpenRISC_1200 label "OpenRISC 1200".
- OpenRISC_1200 sameAs m.0404hlb.
- OpenRISC_1200 sameAs Q7095862.
- OpenRISC_1200 sameAs Q7095862.
- OpenRISC_1200 wasDerivedFrom OpenRISC_1200?oldid=552963844.
- OpenRISC_1200 depiction OR1200.png.
- OpenRISC_1200 isPrimaryTopicOf OpenRISC_1200.
