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- PowerPC_e500 abstract "The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs (from version 2 onwards), 32/32 KiB data and instruction L1 caches and 256, 512 or 1024 KiB L2 frontside cache. Speeds range from 533 MHz up to 1.5 GHz, and the core is designed to be highly configurable and meet the specific needs of embedded applications with features like multi-core operation interface for auxiliary application processing units (APU). e500 powers the high-performance PowerQUICC III system on a chip (SoC) network processors and they all share a common naming scheme, MPC85xx. Freescale's new QorIQ is the evolutionary step from PowerQUICC III and will also be based on e500 cores.".
- PowerPC_e500 wikiPageExternalLink powerquicc.
- PowerPC_e500 wikiPageExternalLink E500CORERM_rev1.pdf.
- PowerPC_e500 wikiPageID "10981835".
- PowerPC_e500 wikiPageRevisionID "550940826".
- PowerPC_e500 hasPhotoCollection PowerPC_e500.
- PowerPC_e500 subject Category:Freescale_microprocessors.
- PowerPC_e500 subject Category:PowerPC_microprocessors.
- PowerPC_e500 comment "The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs (from version 2 onwards), 32/32 KiB data and instruction L1 caches and 256, 512 or 1024 KiB L2 frontside cache.".
- PowerPC_e500 label "PowerPC e500".
- PowerPC_e500 sameAs m.02qx4pg.
- PowerPC_e500 sameAs Q7236216.
- PowerPC_e500 sameAs Q7236216.
- PowerPC_e500 wasDerivedFrom PowerPC_e500?oldid=550940826.
- PowerPC_e500 isPrimaryTopicOf PowerPC_e500.