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- PowerPC_e5500 abstract "The PowerPC e5500 is a 64-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core implements most of the core of the Power ISA v.2.06 with hypervisor support, but not AltiVec. It has a four issue, seven-stage out-of-order pipeline with a double precision FPU, three Integer units, 32/32 KB data and instruction L1 caches, 512 KB private L2 cache per core and up to 2 MB shared L3 cache. Speeds range up to 2.5 GHz, and the core is designed to be highly configurable via the CoreNet fabric and meet the specific needs of embedded applications with features like multi-core operation and interface for auxiliary application processing units (APU).".
- PowerPC_e5500 wikiPageExternalLink phoenix.zhtml?c=196520&p=irol-newsArticle_print&ID=1440425.
- PowerPC_e5500 wikiPageExternalLink 64BTTCHNLGYWP.pdf.
- PowerPC_e5500 wikiPageID "27825850".
- PowerPC_e5500 wikiPageRevisionID "585891046".
- PowerPC_e5500 hasPhotoCollection PowerPC_e5500.
- PowerPC_e5500 subject Category:Freescale_microprocessors.
- PowerPC_e5500 subject Category:PowerPC_microprocessors.
- PowerPC_e5500 comment "The PowerPC e5500 is a 64-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core implements most of the core of the Power ISA v.2.06 with hypervisor support, but not AltiVec. It has a four issue, seven-stage out-of-order pipeline with a double precision FPU, three Integer units, 32/32 KB data and instruction L1 caches, 512 KB private L2 cache per core and up to 2 MB shared L3 cache.".
- PowerPC_e5500 label "PowerPC e5500".
- PowerPC_e5500 sameAs m.0cc5tss.
- PowerPC_e5500 sameAs Q7236215.
- PowerPC_e5500 sameAs Q7236215.
- PowerPC_e5500 wasDerivedFrom PowerPC_e5500?oldid=585891046.
- PowerPC_e5500 isPrimaryTopicOf PowerPC_e5500.