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- S1_Core abstract "S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.The main goal of the project is to keep the S1 Core as simple as possible to encourage developers. The major differences between T1 and S1 include: S1 Core only has one 64-bit SPARC Core (supporting one to four independent threads of execution) instead of eight cores; S1 Core adds a Wishbone bridge, a reset controller and a basic interrupt controller; the S1 Core environment can be run using only free tools on a common x86 Linux machine.".
- S1_Core wikiPageExternalLink project,s1_core.
- S1_Core wikiPageExternalLink s1.sunsource.net.
- S1_Core wikiPageExternalLink ?s1.
- S1_Core wikiPageID "6911994".
- S1_Core wikiPageRevisionID "543435685".
- S1_Core arch SPARC.
- S1_Core designfirm Simply_RISC.
- S1_Core hasPhotoCollection S1_Core.
- S1_Core microarch "V9".
- S1_Core name "S1 Core".
- S1_Core numcores "1".
- S1_Core subject Category:Open_microprocessors.
- S1_Core subject Category:SPARC_microprocessor_architecture.
- S1_Core comment "S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.The main goal of the project is to keep the S1 Core as simple as possible to encourage developers.".
- S1_Core label "S1 Core".
- S1_Core label "S1 Core".
- S1_Core label "S1 Core".
- S1_Core label "S1 Core".
- S1_Core sameAs S1_Core.
- S1_Core sameAs S1_Core.
- S1_Core sameAs m.0gwp3q.
- S1_Core sameAs Q2258330.
- S1_Core sameAs Q2258330.
- S1_Core wasDerivedFrom S1_Core?oldid=543435685.
- S1_Core isPrimaryTopicOf S1_Core.