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• UNIVAC_LARC abstract "The UNIVAC LARC (Livermore Advanced Research Computer) was Remington Rand's first attempt at building a supercomputer. It was designed for multiprocessing with two CPUs (called Computers) and an Input/output (I/O) Processor (called the Processor).Only two LARCs were built:The first was delivered to Livermore in June 1960.The second was delivered to the Navy's David Taylor Model Basin.However both machines only had one Computer, so no multiprocessor LARCs were ever built.The LARC was a decimal mainframe computer with 48 bits per word. It used bi-quinary coded decimal arithmetic with four bits per digit, allowing 11-digit signed numbers. Instructions were 48 bits long, one per word. Every digit in the machine had one parity bit for error checking, meaning every word occupied 60 bits (48 bits for data with 12 bits for parity check). The basic configuration had 26 general purpose registers and could be expanded to 99 general purpose registers. The general-purpose registers had an access time of one microsecond.The basic configuration had one Computer and could be expanded to a multiprocessor with a second Computer.The Processor is an independent CPU (with a different instruction set from the Computers) and provides control for 12 to 24 Magnetic drum storage units, four to forty UNISERVO II tape drives, two Electronic page recorders, one or two High-speed printers, and a High-speed punched card reader.The LARC used core memory banks of 2500 words each, housed four banks per memory cabinet. The basic configuration had eight banks of core (two cabinets), 20000 words. The memory could be expanded to a maximum of 39 banks of core (ten cabinets with one empty bank), 97500 words. The core memory had one parity bit on each digit for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8 microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4-microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another).The data transfer bus connecting the two Computers and the Processor to the core memory was multiplexed to maximize throughput; every 4-microsecond bus cycle was divided into eight 500 nanosecond time slots:Processor - instructions and dataComputer 1 - instructionsComputer 2 - dataI/O DMA Synchronizer - dataNot UsedComputer 2 - instructionsComputer 1 - dataI/O DMA Synchronizer - dataThe core memory system enforces a system of interlocks and priorities to avoid simultaneous access of the same memory bank by multiple sections of the system (the Computers, Processor, and I/O DMA Synchronizers) without conflicts or deadlocks. A memory bank is unavailable for one 4-microsecond cycle after being addressed by any section of the system. If another section attempts to address the same memory bank during this time it is locked out and must wait then try again in the next 4-microsecond cycle. To prevent deadlocks and timeouts in the I/O system the following priorities are enforced:I/O DMA Synchronizer - HighestProcessorComputers - LowestIf a higher priority section is locked out in one 4-microsecond cycle, when it tries again in the next 4-microsecond cycle, all lower-priority sections are prevented from beginning a new cycle on that memory bank until the higher-priority section has completed its access.The LARC was built using surface barrier transistors, which were already obsolete by the time the first system was delivered. The LARC was a very fast computer for its time. Its addition time was 4 microseconds, multiplication time was 8 microseconds, and the division time was 28 microseconds. It was the fastest computer in 1960-1961, until the IBM 7030 took the title.".
• UNIVAC_LARC wikiPageExternalLink BRL61-u3.html.
• UNIVAC_LARC wikiPageExternalLink 41420.
• UNIVAC_LARC wikiPageExternalLink larc.
• UNIVAC_LARC wikiPageID "521318".
• UNIVAC_LARC wikiPageRevisionID "594190175".
• UNIVAC_LARC hasPhotoCollection UNIVAC_LARC.
• UNIVAC_LARC title Mainframe_computer.
• UNIVAC_LARC years "1960".
• UNIVAC_LARC subject Category:1960_introductions.
• UNIVAC_LARC subject Category:Supercomputers.
• UNIVAC_LARC subject Category:Transistorized_computers.
• UNIVAC_LARC subject Category:UNIVAC_mainframe_computers.
• UNIVAC_LARC type Artifact100021939.
• UNIVAC_LARC type Computer103082979.
• UNIVAC_LARC type Device103183080.
• UNIVAC_LARC type DigitalComputer103196324.
• UNIVAC_LARC type Instrumentality103575240.
• UNIVAC_LARC type Machine103699975.
• UNIVAC_LARC type Mainframe103711711.
• UNIVAC_LARC type Object100002684.
• UNIVAC_LARC type PhysicalEntity100001930.
• UNIVAC_LARC type Supercomputer104358117.
• UNIVAC_LARC type Supercomputers.
• UNIVAC_LARC type TransistorizedComputers.
• UNIVAC_LARC type UNIVACMainframeComputers.
• UNIVAC_LARC type Whole100003553.
• UNIVAC_LARC comment "The UNIVAC LARC (Livermore Advanced Research Computer) was Remington Rand's first attempt at building a supercomputer.".
• UNIVAC_LARC label "LARC".
• UNIVAC_LARC label "LARC".
• UNIVAC_LARC label "UNIVAC LARC".
• UNIVAC_LARC label "UNIVAC LARC".
• UNIVAC_LARC sameAs UNIVAC_LARC.
• UNIVAC_LARC sameAs LARC.
• UNIVAC_LARC sameAs LARC.
• UNIVAC_LARC sameAs m.02l26x.
• UNIVAC_LARC sameAs Q694960.
• UNIVAC_LARC sameAs Q694960.
• UNIVAC_LARC sameAs UNIVAC_LARC.
• UNIVAC_LARC wasDerivedFrom UNIVAC_LARC?oldid=594190175.
• UNIVAC_LARC isPrimaryTopicOf UNIVAC_LARC.