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catalog contributor b11384448.
catalog created "2000.".
catalog date "2000".
catalog date "2000.".
catalog dateCopyrighted "2000.".
catalog description "1.1 About Digital Design 1 -- 1.2 Analog versus Digital 3 -- 1.3 Digital Devices 6 -- 1.4 Electronic Aspects of Digital Design 7 -- 1.5 Software Aspects of Digital Design 9 -- 1.6 Integrated Circuits 12 -- 1.7 Programmable Logic Devices 15 -- 1.8 Application-Specific ICs 16 -- 1.9 Printed-Circuit Boards 18 -- 1.10 Digital-Design Levels 18 -- 1.11 Name of the Game 22 -- 1.12 Going Forward 23 -- 2 Number Systems and Codes 25 -- 2.1 Positional Number Systems 26 -- 2.2 Octal and Hexadecimal Numbers 27 -- 2.3 General Positional-Number-System Conversions 29 -- 2.4 Addition and Subtraction of Nondecimal Numbers 32 -- 2.5 Representation of Negative Numbers 34 -- 2.5.1 Signed-Magnitude Representation -- 2.5.2 Complement Number Systems -- 2.5.3 Radix-Complement Representation -- 2.5.4 Two's-Complement Representation -- 2.5.5".
catalog description "2.16 Codes for Serial Data Transmission and Storage 69 -- 2.16.1 Parallel and Serial Data -- 2.16.2 Serial Line Codes -- 3 Digital Circuits 79 -- 3.1 Logic Signals and Gates 80 -- 3.2 Logic Families 84 -- 3.3 CMOS Logic 86 -- 3.3.1 CMOS Logic Levels -- 3.3.2 MOS Transistors -- 3.3.3 Basic CMOS Inverter Circuit -- 3.3.4 CMOS NAND and NOR Gates -- 3.3.5 Fan-In -- 3.3.6 Noninverting Gates -- 3.3.7 CMOS AND-OR-INVERT and OR-AND-INVERT Gates -- 3.4 Electrical Behavior of CMOS Circuits 96 -- 3.4.2 Data Sheets and Specifications -- 3.5 CMOS Steady-State Electrical Behavior 99 -- 3.5.1 Logic Levels and Noise Margins -- 3.5.2 Circuit Behavior with Resistive Loads -- 3.5.3 Circuit Behavior with Nonideal Inputs -- 3.5.4 Fanout -- 3.5.5 Effects of Loading -- 3.5.6 Unused Inputs -- 3.5.7 Current Spikes and Decoupling Capacitors -- 3.5.8 How to Destroy a CMOS Device -- 3.6".
catalog description "3.10.4 Unused Inputs -- 3.10.5 Additional TTL Gate Types -- 3.11 TTL Families 166 -- 3.11.1 Early TTL Families -- 3.11.2 Schottky TTL Families -- 3.11.3 Characteristics of TTL Families -- 3.11.4 A TTL Data Sheet -- 3.12 CMOS/TTL Interfacing 170 -- 3.13 Low-Voltage CMOS Logic and Interfacing 171 -- 3.13.1 3.3-V LVTTL and LVCMOS Logic -- 3.13.2 5-V Tolerant Inputs -- 3.13.3 5-V Tolerant Outputs -- 3.13.4 TTL/LVTTL Interfacing Summary -- 3.13.5 2.5-V and 1.8-V Logic -- 3.14 Emitter-Coupled Logic 175 -- 3.14.1 Basic CML Circuit -- 3.14.2 ECL 10K/10H Families -- 3.14.3 ECL 100K Family -- 3.14.4 Positive ECL (PECL) -- 4 Combinational Logic Design Principles 193 -- 4.1 Switching Algebra 194 -- 4.1.1 Axioms -- 4.1.2 Single-Variable Theorems -- 4.1.3 Two- and Three-Variable Theorems -- 4.1.4 n-Variable Theorems -- 4.1.5 Duality -- 4.1.6".
catalog description "5.9.5 Comparators in ABEL and PLDs -- 5.9.6 Comparators in VHDL -- 5.10 Adders, Subtractors, and ALUs 430 -- 5.10.1 Half Adders and Full Adders -- 5.10.2 Ripple Adders -- 5.10.3 Subtractors -- 5.10.4 Carry Lookahead Adders -- 5.10.5 MSI Adders -- 5.10.6 MSI Arithmetic and Logic Units -- 5.10.7 Group-Carry Lookahead -- 5.10.8 Adders in ABEL and PLDs -- 5.10.9 Adders in VHDL -- 5.11 Combinational Multipliers 446 -- 5.11.1 Combinational Multiplier Structures -- 5.11.2 Multiplication in ABEL and PLDs -- 5.11.3 Multiplication in VHDL -- 6 Combinational-Circuit Design Examples 467 -- 6.1 Building-Block Design Examples 468 -- 6.1.1 Barrel Shifter -- 6.1.2 Simple Floating-Point Encoder -- 6.1.3 Dual-Priority Encoder -- 6.1.4 Cascading Comparators -- 6.1.5 Mode-Dependent Comparator -- 6.2 Design Examples Using ABEL and PLDs 479 -- 6.2.1 Barrel Shifter -- 6.2.2".
catalog description "ABEL Program Structure -- 4.6.2 ABEL Compiler Operation -- 4.6.3 WHEN Statements and Equation Blocks -- 4.6.4 Truth Tables -- 4.6.5 Ranges, Sets, and Relations -- 4.6.6 Don't-Care Inputs -- 4.6.7 Test Vectors -- 4.7 VHDL Hardware Description Language 264 -- 4.7.1 Design Flow -- 4.7.2 Program Structure -- 4.7.3 Types and Constants -- 4.7.4 Functions and Procedures -- 4.7.5 Libraries and Packages -- 4.7.6 Structural Design Elements -- 4.7.7 Dataflow Design Elements -- 4.7.8 Behavioral Design Elements -- 4.7.9 Time Dimension and Simulation -- 4.7.10 Synthesis -- 5 Combinational Logic Design Practices 311 -- 5.1 Documentation Standards 312 -- 5.1.1 Block Diagrams -- 5.1.2 Gate Symbols -- 5.1.3 Signal Names and Active Levels -- 5.1.4 Active Levels for Pins -- 5.1.5 Bubble-to-Bubble Logic Design -- 5.1.6 Drawing Layout -- 5.1.7 Buses -- 5.1.8".
catalog description "Additional Schematic Information -- 5.2 Circuit Timing 330 -- 5.2.1 Timing Diagrams -- 5.2.2 Propagation Delay -- 5.2.3 Timing Specifications -- 5.2.4 Timing Analysis -- 5.2.5 Timing Analysis Tools -- 5.3 Combinational PLDs 337 -- 5.3.1 Programmable Logic Arrays -- 5.3.2 Programmable Array Logic Devices -- 5.3.3 Generic Array Logic Devices -- 5.3.4 Bipolar PLD Circuits -- 5.3.5 CMOS PLD Circuits -- 5.3.6 Device Programming and Testing -- 5.4 Decoders 351 -- 5.4.1 Binary Decoders -- 5.4.2 Logic Symbols for Larger-Scale Elements -- 5.4.3 74[times]139 Dual 2-to-4 Decoder -- 5.4.4 74[times]138 3-to-8 Decoder -- 5.4.5 Cascading Binary Decoders -- 5.4.6 Decoders in ABEL and PLDs -- 5.4.7 Decoders in VHDL -- 5.4.8 Seven-Segment Decoders -- 5.5 Encoders 376 -- 5.5.1 Priority Encoders -- 5.5.2 74[times]148 Priority Encoder -- 5.5.3 Encoders in ABEL and PLDs -- 5.5.4".
catalog description "CMOS Dynamic Electrical Behavior 113 -- 3.6.1 Transition Time -- 3.6.2 Propagation Delay -- 3.6.3 Power Consumption -- 3.7 Other CMOS Input and Output Structures 123 -- 3.7.1 Transmission Gates -- 3.7.2 Schmitt-Trigger Inputs -- 3.7.3 Three-State Outputs -- 3.7.4 Open-Drain Outputs -- 3.7.5 Driving LEDs -- 3.7.6 Multisource Buses -- 3.7.7 Wired Logic -- 3.7.8 Pull-Up Resistors -- 3.8 CMOS Logic Families 135 -- 3.8.1 HC and HCT -- 3.8.2 VHC and VHCT -- 3.8.3 HC, HCT, VHC, and VHCT Electrical Characteristics -- 3.8.4 FCT and FCT-T -- 3.8.5 FCT-T Electrical Characteristics -- 3.9 Bipolar Logic 145 -- 3.9.1 Diodes -- 3.9.2 Diode Logic -- 3.9.3 Bipolar Junction Transistors -- 3.9.4 Transistor Logic Inverter -- 3.9.5 Schottky Transistors -- 3.10 Transistor-Transistor Logic 156 -- 3.10.1 Basic TTL NAND Gate -- 3.10.2 Logic Levels and Noise Margins -- 3.10.3 Fanout --".
catalog description "Diminished Radix-Complement Representation -- 2.5.6 Ones'-Complement Representation -- 2.5.7 Excess Representations -- 2.6 Two's-Complement Addition and Subtraction 39 -- 2.6.1 Addition Rules -- 2.6.2 A Graphical View -- 2.6.3 Overflow -- 2.6.4 Subtraction Rules -- 2.6.5 Two's-Complement and Unsigned Binary Numbers -- 2.7 Ones'-Complement Addition and Subtraction 44 -- 2.8 Binary Multiplication 45 -- 2.9 Binary Division 47 -- 2.10 Binary Codes for Decimal Numbers 48 -- 2.11 Gray Code 51 -- 2.12 Character Codes 53 -- 2.13 Codes for Actions, Conditions, and States 53 -- 2.14 n-Cubes and Distance 57 -- 2.15 Codes for Detecting and Correcting Errors 58 -- 2.15.1 Error-Detecting Codes -- 2.15.2 Error-Correcting and Multiple-Error-Detecting Codes -- 2.15.3 Hamming Codes -- 2.15.4 CRC Codes -- 2.15.5 Two-Dimensional Codes -- 2.15.6 Checksum Codes -- 2.15.7 m-out-of-n Codes --".
catalog description "Encoders in VHDL -- 5.6 Three-State Devices 385 -- 5.6.1 Three-State Buffers -- 5.6.2 Standard SSI and MSI Three-State Buffers -- 5.6.3 Three-State Outputs in ABEL and PLDs -- 5.6.4 Three-State Outputs in VHDL -- 5.7 Multiplexers 398 -- 5.7.1 Standard MSI Multiplexers -- 5.7.2 Expanding Multiplexers -- 5.7.3 Multiplexers, Demultiplexers, and Buses -- 5.7.4 Multiplexers in ABEL and PLDs -- 5.7.5 Multiplexers in VHDL -- 5.8 Exclusive-OR Gates and Parity Circuits 410 -- 5.8.1 Exclusive-OR and Exclusive-NOR Gates -- 5.8.2 Parity Circuits -- 5.8.3 74x280 9-Bit Parity Generator -- 5.8.4S Parity-Checking Applications -- 5.8.5 Exclusive-OR Gates and Parity Circuits in ABEL and PLDs -- 5.8.6 Exclusive-OR Gates and Parity Circuits in VHDL -- 5.9 Comparators 419 -- 5.9.1 Comparator Structure -- 5.9.2 Iterative Circuits -- 5.9.3 An Iterative Comparator Circuit -- 5.9.4 Standard MSI Comparators --".
catalog description "Includes bibliographical references and index.".
catalog description "Simple Floating-Point Encoder -- 6.2.3 Dual-Priority Encoder -- 6.2.4 Cascading Comparators -- 6.2.5 Mode-Dependent Comparator -- 6.2.6 Ones Counter -- 6.2.7 Tic-Tac-Toe -- 6.3 Design Examples Using VHDL 500 -- 6.3.1 Barrel Shifter -- 6.3.2 Simple Floating-Point Encoder -- 6.3.3 Dual-Priority Encoder -- 6.3.4 Cascading Comparators -- 6.3.5 Mode-Dependent Comparator -- 6.3.6 Ones Counter -- 6.3.7 Tic-Tac-Toe -- 7 Sequential Logic Design Principles 529 -- 7.1 Bistable Elements 531 -- 7.1.1 Digital Analysis -- 7.1.2 Analog Analysis -- 7.1.3 Metastable Behavior -- 7.2 Latches and Flip-Flops 534 -- 7.2.1 S-R Latch -- 7.2.2 S-R Latch -- 7.2.3 S-R Latch with Enable.".
catalog description "Standard Representations of Logic Functions -- 4.2 Combinational-Circuit Analysis 209 -- 4.3 Combinational-Circuit Synthesis 215 -- 4.3.1 Circuit Descriptions and Designs -- 4.3.2 Circuit Manipulations -- 4.3.3 Combinational-Circuit Minimization -- 4.3.4 Karnaugh Maps -- 4.3.5 Minimizing Sums of Products -- 4.3.6 Simplifying Products of Sums -- 4.3.7 "Don't-Care" Input Combinations -- 4.3.8 Multiple-Output Minimization -- 4.4 Programmed Minimization Methods 236 -- 4.4.1 Representation of Product Terms -- 4.4.2 Finding Prime Implicants by Combining Product Terms -- 4.4.3 Finding a Minimal Cover Using a Prime-Implicant Table -- 4.4.4 Other Minimization Methods -- 4.5 Timing Hazards 244 -- 4.5.1 Static Hazards -- 4.5.2 Finding Static Hazards Using Maps -- 4.5.3 Dynamic Hazards -- 4.5.4 Designing Hazard-Free Circuits -- 4.6 ABEL Hardware Description Language 249 -- 4.6.1".
catalog extent "xxiii, 946 p. :".
catalog identifier "0137691912".
catalog issued "2000".
catalog issued "2000.".
catalog language "eng".
catalog publisher "Upper Saddle River, N.J. : Prentice Hall,".
catalog subject "621.39/5 21".
catalog subject "Digital integrated circuits Design and construction.".
catalog subject "TK7874.65 .W34 2000".
catalog tableOfContents "1.1 About Digital Design 1 -- 1.2 Analog versus Digital 3 -- 1.3 Digital Devices 6 -- 1.4 Electronic Aspects of Digital Design 7 -- 1.5 Software Aspects of Digital Design 9 -- 1.6 Integrated Circuits 12 -- 1.7 Programmable Logic Devices 15 -- 1.8 Application-Specific ICs 16 -- 1.9 Printed-Circuit Boards 18 -- 1.10 Digital-Design Levels 18 -- 1.11 Name of the Game 22 -- 1.12 Going Forward 23 -- 2 Number Systems and Codes 25 -- 2.1 Positional Number Systems 26 -- 2.2 Octal and Hexadecimal Numbers 27 -- 2.3 General Positional-Number-System Conversions 29 -- 2.4 Addition and Subtraction of Nondecimal Numbers 32 -- 2.5 Representation of Negative Numbers 34 -- 2.5.1 Signed-Magnitude Representation -- 2.5.2 Complement Number Systems -- 2.5.3 Radix-Complement Representation -- 2.5.4 Two's-Complement Representation -- 2.5.5".
catalog tableOfContents "2.16 Codes for Serial Data Transmission and Storage 69 -- 2.16.1 Parallel and Serial Data -- 2.16.2 Serial Line Codes -- 3 Digital Circuits 79 -- 3.1 Logic Signals and Gates 80 -- 3.2 Logic Families 84 -- 3.3 CMOS Logic 86 -- 3.3.1 CMOS Logic Levels -- 3.3.2 MOS Transistors -- 3.3.3 Basic CMOS Inverter Circuit -- 3.3.4 CMOS NAND and NOR Gates -- 3.3.5 Fan-In -- 3.3.6 Noninverting Gates -- 3.3.7 CMOS AND-OR-INVERT and OR-AND-INVERT Gates -- 3.4 Electrical Behavior of CMOS Circuits 96 -- 3.4.2 Data Sheets and Specifications -- 3.5 CMOS Steady-State Electrical Behavior 99 -- 3.5.1 Logic Levels and Noise Margins -- 3.5.2 Circuit Behavior with Resistive Loads -- 3.5.3 Circuit Behavior with Nonideal Inputs -- 3.5.4 Fanout -- 3.5.5 Effects of Loading -- 3.5.6 Unused Inputs -- 3.5.7 Current Spikes and Decoupling Capacitors -- 3.5.8 How to Destroy a CMOS Device -- 3.6".
catalog tableOfContents "3.10.4 Unused Inputs -- 3.10.5 Additional TTL Gate Types -- 3.11 TTL Families 166 -- 3.11.1 Early TTL Families -- 3.11.2 Schottky TTL Families -- 3.11.3 Characteristics of TTL Families -- 3.11.4 A TTL Data Sheet -- 3.12 CMOS/TTL Interfacing 170 -- 3.13 Low-Voltage CMOS Logic and Interfacing 171 -- 3.13.1 3.3-V LVTTL and LVCMOS Logic -- 3.13.2 5-V Tolerant Inputs -- 3.13.3 5-V Tolerant Outputs -- 3.13.4 TTL/LVTTL Interfacing Summary -- 3.13.5 2.5-V and 1.8-V Logic -- 3.14 Emitter-Coupled Logic 175 -- 3.14.1 Basic CML Circuit -- 3.14.2 ECL 10K/10H Families -- 3.14.3 ECL 100K Family -- 3.14.4 Positive ECL (PECL) -- 4 Combinational Logic Design Principles 193 -- 4.1 Switching Algebra 194 -- 4.1.1 Axioms -- 4.1.2 Single-Variable Theorems -- 4.1.3 Two- and Three-Variable Theorems -- 4.1.4 n-Variable Theorems -- 4.1.5 Duality -- 4.1.6".
catalog tableOfContents "5.9.5 Comparators in ABEL and PLDs -- 5.9.6 Comparators in VHDL -- 5.10 Adders, Subtractors, and ALUs 430 -- 5.10.1 Half Adders and Full Adders -- 5.10.2 Ripple Adders -- 5.10.3 Subtractors -- 5.10.4 Carry Lookahead Adders -- 5.10.5 MSI Adders -- 5.10.6 MSI Arithmetic and Logic Units -- 5.10.7 Group-Carry Lookahead -- 5.10.8 Adders in ABEL and PLDs -- 5.10.9 Adders in VHDL -- 5.11 Combinational Multipliers 446 -- 5.11.1 Combinational Multiplier Structures -- 5.11.2 Multiplication in ABEL and PLDs -- 5.11.3 Multiplication in VHDL -- 6 Combinational-Circuit Design Examples 467 -- 6.1 Building-Block Design Examples 468 -- 6.1.1 Barrel Shifter -- 6.1.2 Simple Floating-Point Encoder -- 6.1.3 Dual-Priority Encoder -- 6.1.4 Cascading Comparators -- 6.1.5 Mode-Dependent Comparator -- 6.2 Design Examples Using ABEL and PLDs 479 -- 6.2.1 Barrel Shifter -- 6.2.2".
catalog tableOfContents "ABEL Program Structure -- 4.6.2 ABEL Compiler Operation -- 4.6.3 WHEN Statements and Equation Blocks -- 4.6.4 Truth Tables -- 4.6.5 Ranges, Sets, and Relations -- 4.6.6 Don't-Care Inputs -- 4.6.7 Test Vectors -- 4.7 VHDL Hardware Description Language 264 -- 4.7.1 Design Flow -- 4.7.2 Program Structure -- 4.7.3 Types and Constants -- 4.7.4 Functions and Procedures -- 4.7.5 Libraries and Packages -- 4.7.6 Structural Design Elements -- 4.7.7 Dataflow Design Elements -- 4.7.8 Behavioral Design Elements -- 4.7.9 Time Dimension and Simulation -- 4.7.10 Synthesis -- 5 Combinational Logic Design Practices 311 -- 5.1 Documentation Standards 312 -- 5.1.1 Block Diagrams -- 5.1.2 Gate Symbols -- 5.1.3 Signal Names and Active Levels -- 5.1.4 Active Levels for Pins -- 5.1.5 Bubble-to-Bubble Logic Design -- 5.1.6 Drawing Layout -- 5.1.7 Buses -- 5.1.8".
catalog tableOfContents "Additional Schematic Information -- 5.2 Circuit Timing 330 -- 5.2.1 Timing Diagrams -- 5.2.2 Propagation Delay -- 5.2.3 Timing Specifications -- 5.2.4 Timing Analysis -- 5.2.5 Timing Analysis Tools -- 5.3 Combinational PLDs 337 -- 5.3.1 Programmable Logic Arrays -- 5.3.2 Programmable Array Logic Devices -- 5.3.3 Generic Array Logic Devices -- 5.3.4 Bipolar PLD Circuits -- 5.3.5 CMOS PLD Circuits -- 5.3.6 Device Programming and Testing -- 5.4 Decoders 351 -- 5.4.1 Binary Decoders -- 5.4.2 Logic Symbols for Larger-Scale Elements -- 5.4.3 74[times]139 Dual 2-to-4 Decoder -- 5.4.4 74[times]138 3-to-8 Decoder -- 5.4.5 Cascading Binary Decoders -- 5.4.6 Decoders in ABEL and PLDs -- 5.4.7 Decoders in VHDL -- 5.4.8 Seven-Segment Decoders -- 5.5 Encoders 376 -- 5.5.1 Priority Encoders -- 5.5.2 74[times]148 Priority Encoder -- 5.5.3 Encoders in ABEL and PLDs -- 5.5.4".
catalog tableOfContents "CMOS Dynamic Electrical Behavior 113 -- 3.6.1 Transition Time -- 3.6.2 Propagation Delay -- 3.6.3 Power Consumption -- 3.7 Other CMOS Input and Output Structures 123 -- 3.7.1 Transmission Gates -- 3.7.2 Schmitt-Trigger Inputs -- 3.7.3 Three-State Outputs -- 3.7.4 Open-Drain Outputs -- 3.7.5 Driving LEDs -- 3.7.6 Multisource Buses -- 3.7.7 Wired Logic -- 3.7.8 Pull-Up Resistors -- 3.8 CMOS Logic Families 135 -- 3.8.1 HC and HCT -- 3.8.2 VHC and VHCT -- 3.8.3 HC, HCT, VHC, and VHCT Electrical Characteristics -- 3.8.4 FCT and FCT-T -- 3.8.5 FCT-T Electrical Characteristics -- 3.9 Bipolar Logic 145 -- 3.9.1 Diodes -- 3.9.2 Diode Logic -- 3.9.3 Bipolar Junction Transistors -- 3.9.4 Transistor Logic Inverter -- 3.9.5 Schottky Transistors -- 3.10 Transistor-Transistor Logic 156 -- 3.10.1 Basic TTL NAND Gate -- 3.10.2 Logic Levels and Noise Margins -- 3.10.3 Fanout --".
catalog tableOfContents "Diminished Radix-Complement Representation -- 2.5.6 Ones'-Complement Representation -- 2.5.7 Excess Representations -- 2.6 Two's-Complement Addition and Subtraction 39 -- 2.6.1 Addition Rules -- 2.6.2 A Graphical View -- 2.6.3 Overflow -- 2.6.4 Subtraction Rules -- 2.6.5 Two's-Complement and Unsigned Binary Numbers -- 2.7 Ones'-Complement Addition and Subtraction 44 -- 2.8 Binary Multiplication 45 -- 2.9 Binary Division 47 -- 2.10 Binary Codes for Decimal Numbers 48 -- 2.11 Gray Code 51 -- 2.12 Character Codes 53 -- 2.13 Codes for Actions, Conditions, and States 53 -- 2.14 n-Cubes and Distance 57 -- 2.15 Codes for Detecting and Correcting Errors 58 -- 2.15.1 Error-Detecting Codes -- 2.15.2 Error-Correcting and Multiple-Error-Detecting Codes -- 2.15.3 Hamming Codes -- 2.15.4 CRC Codes -- 2.15.5 Two-Dimensional Codes -- 2.15.6 Checksum Codes -- 2.15.7 m-out-of-n Codes --".
catalog tableOfContents "Encoders in VHDL -- 5.6 Three-State Devices 385 -- 5.6.1 Three-State Buffers -- 5.6.2 Standard SSI and MSI Three-State Buffers -- 5.6.3 Three-State Outputs in ABEL and PLDs -- 5.6.4 Three-State Outputs in VHDL -- 5.7 Multiplexers 398 -- 5.7.1 Standard MSI Multiplexers -- 5.7.2 Expanding Multiplexers -- 5.7.3 Multiplexers, Demultiplexers, and Buses -- 5.7.4 Multiplexers in ABEL and PLDs -- 5.7.5 Multiplexers in VHDL -- 5.8 Exclusive-OR Gates and Parity Circuits 410 -- 5.8.1 Exclusive-OR and Exclusive-NOR Gates -- 5.8.2 Parity Circuits -- 5.8.3 74x280 9-Bit Parity Generator -- 5.8.4S Parity-Checking Applications -- 5.8.5 Exclusive-OR Gates and Parity Circuits in ABEL and PLDs -- 5.8.6 Exclusive-OR Gates and Parity Circuits in VHDL -- 5.9 Comparators 419 -- 5.9.1 Comparator Structure -- 5.9.2 Iterative Circuits -- 5.9.3 An Iterative Comparator Circuit -- 5.9.4 Standard MSI Comparators --".
catalog tableOfContents "Simple Floating-Point Encoder -- 6.2.3 Dual-Priority Encoder -- 6.2.4 Cascading Comparators -- 6.2.5 Mode-Dependent Comparator -- 6.2.6 Ones Counter -- 6.2.7 Tic-Tac-Toe -- 6.3 Design Examples Using VHDL 500 -- 6.3.1 Barrel Shifter -- 6.3.2 Simple Floating-Point Encoder -- 6.3.3 Dual-Priority Encoder -- 6.3.4 Cascading Comparators -- 6.3.5 Mode-Dependent Comparator -- 6.3.6 Ones Counter -- 6.3.7 Tic-Tac-Toe -- 7 Sequential Logic Design Principles 529 -- 7.1 Bistable Elements 531 -- 7.1.1 Digital Analysis -- 7.1.2 Analog Analysis -- 7.1.3 Metastable Behavior -- 7.2 Latches and Flip-Flops 534 -- 7.2.1 S-R Latch -- 7.2.2 S-R Latch -- 7.2.3 S-R Latch with Enable.".
catalog tableOfContents "Standard Representations of Logic Functions -- 4.2 Combinational-Circuit Analysis 209 -- 4.3 Combinational-Circuit Synthesis 215 -- 4.3.1 Circuit Descriptions and Designs -- 4.3.2 Circuit Manipulations -- 4.3.3 Combinational-Circuit Minimization -- 4.3.4 Karnaugh Maps -- 4.3.5 Minimizing Sums of Products -- 4.3.6 Simplifying Products of Sums -- 4.3.7 "Don't-Care" Input Combinations -- 4.3.8 Multiple-Output Minimization -- 4.4 Programmed Minimization Methods 236 -- 4.4.1 Representation of Product Terms -- 4.4.2 Finding Prime Implicants by Combining Product Terms -- 4.4.3 Finding a Minimal Cover Using a Prime-Implicant Table -- 4.4.4 Other Minimization Methods -- 4.5 Timing Hazards 244 -- 4.5.1 Static Hazards -- 4.5.2 Finding Static Hazards Using Maps -- 4.5.3 Dynamic Hazards -- 4.5.4 Designing Hazard-Free Circuits -- 4.6 ABEL Hardware Description Language 249 -- 4.6.1".
catalog title "Digital design : principles and practices / John F. Wakerly.".
catalog type "text".