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catalog abstract "Thisworkshopisthetenthinaseriesofinternationalworkshops. Thisyear ittakesplaceinG¨ottingen,Germany,andisorganizedbytheUniversityof Hannover. G¨ottingenhasonethemostfamousGermanuniversities,whereverywell knownscientistslikeLichtenberg,Hilbert,GaussandvonNeumannstudied, workedandtaught. ItalsohostsseveralresearchinstitutesoftheMax-Planck- Society. The?rstelectronictubecalculatorG1wasbuiltinG¨ottingenin1952 byH. Billing. Additionally,G¨ottingenwasselectedbecauseitisadjacenttothe worldexpositionEXPO2000inHannoverwhichgivesanoutlookintothe21st centurycoveringthemajortopicsofhumankind,natureandtechnology. WithrespecttotheseinspiringsurroundingsthetechnicalprogramofPAT- MOS2000includes10sessionsdedicatedtomostimportantsubjectsofpower andtimingmodeling,optimizationandsimulationatthedawnofthe21stc- tury. ThefourinvitedtalksaddresstheEuropeanresearchactivitiesinthewo- shop?elds,theevolvingneedsforminimalpowerconsumptionintheareaof wirelessandchipcardapplicationsanddesignmethodologiesofveryhighly- tegratedmultimediaprocessors. Theworkshopisaresultofthejointworkofalargenumberofindividuals, whocannotallbementionedhere. Inparticular,wewouldliketoacknowledge theoutstandingworkofthereviewers,whodidacompetentjobinatimely manner. Wealsohavetothankthemembersofthelocalorganizingcommittee fortheire?ortinenablingtheconferencetorunsmoothly. Finally,wegratefully acknowledgethesupportofallorganizationsandinstitutionssponsoringthe conference. September2000 PeterPirsch ErichBarke DimitriosSoudris Organization OrganizationCommitee GeneralCoChairs: PeterPirsch(UniversityofHannover,Germany) ErichBarke(UniversityofHannover,Germany) ProgramChair: DimitriosSoudris (DemocritusUniversityofThrace,Greece) FinanceChair: LarsHedrich(UniversityofHannover,Germany) PublicationChair: AchimFreimann (UniversityofHannover,Germany) Audio-VisualChair: J¨orgAbke(UniversityofHannover,Germany) LocalArrangementsChair: CarstenReuter(UniversityofHannover,Germany) ProgramCommitee D. Auvergne(UniversityofMontpellier,France) J. Bormans(IMEC,Belgium) J. Figueras(UniversityofCatalunya,Spain) C. E. Goutis(UniversityofPatras,Greece) A. Guyot(INPGGrenoble,France) R. Hartenstein(UniversityofKaiserslautern,Germany) S. Jones(UniversityofLoughborough,UnitedKingdom) P. Larsson-Edefors(UniversityofLink¨oping,Sweden) E. Macii(PolytechnicofTorino,Italy) V. Moshnyaga(UniversityofFukuoka,Japan) W. Nebel(UniversityofOldenburg,Germany) J. A. Nossek(TechnicalUniversityofMunc ¨ hen,Germany) A. Nunez(UniversityofLasPalmas,Spain) M. Papaefthymiou(UniversityofMichigan,UnitedStates) M. Pedram(UniversityofSouthernCalifornia,UnitedStates) H. P?eiderer(UniversityofUlm,Germany) C. Piguet(CSEM,Switzerland) R. Reis(UniversityofPortoAlegre,Brazil) M. Robert(UniversityofMontpellier,France) A. Rubio(UniversityofCatalunya,Spain) J. Sparsø(TechnicalUniversityofDenmark,Denmark) A. Stempkowsky(AcademyofSciences,Russia) T. Stouraitis(UniversityofPatras,Greece) J. F. M. Theeuwen(Philips,TheNetherlands) A. -M. Trullemans-Anckaert(UniversityofLouvain,Belgium) R. Zafalon(STMicroelectronics,Italy) VIII Organization SteeringCommitee D. Auvergne(UniversityofMontpellier,France) R. Hartenstein(UniversityofKaiserslautern,Germany) W. Nebel(UniversityofOldenburg,Germany) C. Piguet(CSEM,Switzerland) A. Rubio(UniversityofCatalunya,Spain) J. Sparsø(TechnicalUniversityofDenmark,Denmark) A. -M. Trullemans-Anckaert(UniversityofLouvain,Belgium) SponsoringInstitutions EuropeanCommissionDirectorate–GeneralInformationSociety IEEECircuitsandSystemsSociety TableofContents Opening Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 R. vanLeuken,R. Nouta,A. deGraf(DelftUniversityofTechnology, TheNetherlands) RTL Power Modeling Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. . . . . . . . . . . . . . . . . . 3 M. Anton,M. Chinosi,D. Sirtori,R. Zafalon(STMicroelectronics, Italy) Power Models for Semi-autonomous RTL Macros . . . . . . . . . . . . . . . . . . . . . . 14 A. Bogliolo(UniversityofFerrara,Italy) E. Macii,V. Mihailovici,M. Poncino(PolytechnicalUniversityofTorino, Italy) Power Macro-Modelling for Firm-Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 G. Jochens,L. Kruse,E. Schmidt,A. Stammermann,W. Nebel (OFFISResearchInstitute,Oldenburg,Germany) RTL Estimation of Steering Logic Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 C. Anton,P. Civera,I. Colonescu,E. Macii,M. Poncino (PolytechnicalUniversityofTorino,Italy) A. Bogliolo(UniversityofFerrara,Italy) PowerEstimationandOptimization Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 N. D. Zervas,S. Theoharis,A. P. Kakaroudas,G. Theodoridis, C. E. Goutis(UniversityofPatras,Greece) D.".
catalog contributor b11941716.
catalog contributor b11941717.
catalog contributor b11941718.
catalog contributor b11941719.
catalog created "2000.".
catalog date "2000".
catalog date "2000.".
catalog dateCopyrighted "2000.".
catalog description "Cost-Efficient C-Level Design of an MPEG-4 Video Decoder -- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications -- AdiabaticDesign and ArithmeticModules -- Design of Reversible Logic Circuits by Means of Control Gates -- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates -- An Adiabatic Multiplier -- Logarithmic Number System for Low-Power Arithmetic -- Analog-Digital Circuits Modeling -- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits -- PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits -- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits -- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.".
catalog description "Includes bibliographical references and index.".
catalog description "Nebel (OFFISResearchInstitute,Oldenburg,Germany) RTL Estimation of Steering Logic Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 C. Anton,P. Civera,I. Colonescu,E. Macii,M. Poncino (PolytechnicalUniversityofTorino,Italy) A. Bogliolo(UniversityofFerrara,Italy) PowerEstimationandOptimization Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 N. D. Zervas,S. Theoharis,A. P. Kakaroudas,G. Theodoridis, C. E. Goutis(UniversityofPatras,Greece) D.".
catalog description "Nossek(TechnicalUniversityofMunc ¨ hen,Germany) A. Nunez(UniversityofLasPalmas,Spain) M. Papaefthymiou(UniversityofMichigan,UnitedStates) M. Pedram(UniversityofSouthernCalifornia,UnitedStates) H. P?eiderer(UniversityofUlm,Germany) C. Piguet(CSEM,Switzerland) R. Reis(UniversityofPortoAlegre,Brazil) M. Robert(UniversityofMontpellier,France) A. Rubio(UniversityofCatalunya,Spain) J. Sparsø(TechnicalUniversityofDenmark,Denmark) A. Stempkowsky(AcademyofSciences,Russia) T. Stouraitis(UniversityofPatras,Greece) J. F. M. Theeuwen(Philips,TheNetherlands) A. -M. Trullemans-Anckaert(UniversityofLouvain,Belgium) R. Zafalon(STMicroelectronics,Italy) VIII Organization SteeringCommitee D. Auvergne(UniversityofMontpellier,France) R. Hartenstein(UniversityofKaiserslautern,Germany) W. Nebel(UniversityofOldenburg,Germany) C. Piguet(CSEM,Switzerland) A. Rubio(UniversityofCatalunya,Spain) J. Sparsø(TechnicalUniversityofDenmark,Denmark) A. -M. ".
catalog description "Opening -- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action -- RTL Power Modeling -- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques -- Power Models for Semi-autonomous RTL Macros -- Power Macro-Modelling for Firm-Macro -- RTL Estimation of Steering Logic Power -- Power Estimation and Optimization -- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers -- Framework for High-Level Power Estimation of Signal Processing Architectures -- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses -- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions -- System-Level Design -- A Holistic Approach to System Level Energy Optimization -- Early Power Estimation for System-on-Chip Designs -- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures -- ".
catalog description "September2000 PeterPirsch ErichBarke DimitriosSoudris Organization OrganizationCommitee GeneralCoChairs: PeterPirsch(UniversityofHannover,Germany) ErichBarke(UniversityofHannover,Germany) ProgramChair: DimitriosSoudris (DemocritusUniversityofThrace,Greece) FinanceChair: LarsHedrich(UniversityofHannover,Germany) PublicationChair: AchimFreimann (UniversityofHannover,Germany) Audio-VisualChair: J¨orgAbke(UniversityofHannover,Germany) LocalArrangementsChair: CarstenReuter(UniversityofHannover,Germany) ProgramCommitee D. Auvergne(UniversityofMontpellier,France) J. Bormans(IMEC,Belgium) J. Figueras(UniversityofCatalunya,Spain) C. E. Goutis(UniversityofPatras,Greece) A. Guyot(INPGGrenoble,France) R. Hartenstein(UniversityofKaiserslautern,Germany) S. Jones(UniversityofLoughborough,UnitedKingdom) P. Larsson-Edefors(UniversityofLink¨oping,Sweden) E. Macii(PolytechnicofTorino,Italy) V. Moshnyaga(UniversityofFukuoka,Japan) W. Nebel(UniversityofOldenburg,Germany) J. A. ".
catalog description "ThefourinvitedtalksaddresstheEuropeanresearchactivitiesinthewo- shop?elds,theevolvingneedsforminimalpowerconsumptionintheareaof wirelessandchipcardapplicationsanddesignmethodologiesofveryhighly- tegratedmultimediaprocessors. Theworkshopisaresultofthejointworkofalargenumberofindividuals, whocannotallbementionedhere. Inparticular,wewouldliketoacknowledge theoutstandingworkofthereviewers,whodidacompetentjobinatimely manner. Wealsohavetothankthemembersofthelocalorganizingcommittee fortheire?ortinenablingtheconferencetorunsmoothly. Finally,wegratefully acknowledgethesupportofallorganizationsandinstitutionssponsoringthe conference. ".
catalog description "Thisworkshopisthetenthinaseriesofinternationalworkshops. Thisyear ittakesplaceinG¨ottingen,Germany,andisorganizedbytheUniversityof Hannover. G¨ottingenhasonethemostfamousGermanuniversities,whereverywell knownscientistslikeLichtenberg,Hilbert,GaussandvonNeumannstudied, workedandtaught. ItalsohostsseveralresearchinstitutesoftheMax-Planck- Society. The?rstelectronictubecalculatorG1wasbuiltinG¨ottingenin1952 byH. Billing. Additionally,G¨ottingenwasselectedbecauseitisadjacenttothe worldexpositionEXPO2000inHannoverwhichgivesanoutlookintothe21st centurycoveringthemajortopicsofhumankind,natureandtechnology. WithrespecttotheseinspiringsurroundingsthetechnicalprogramofPAT- MOS2000includes10sessionsdedicatedtomostimportantsubjectsofpower andtimingmodeling,optimizationandsimulationatthedawnofthe21stc- tury. ".
catalog description "Transistor-Level Modeling -- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design -- Impact of Voltage Scaling on Glitch Power Consumption -- Degradation Delay Model Extension to CMOS Gates -- Second Generation Delay Model for Submicron CMOS Process -- Asynchronous Circuit Design -- Semi-modular Latch Chains for Asynchronous Circuit Design -- Asynchronous First-in First-out Queues -- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance -- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder -- Power Efficient Technologies -- Low Power Design Techniques for Contactless Chipcards -- Dynamic Memory Design for Low Data-Retention Power -- Double-Latch Clocking Scheme for Low-Power I.P. Cores -- Design of Multimedia Processing Applications -- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip -- ".
catalog description "Trullemans-Anckaert(UniversityofLouvain,Belgium) SponsoringInstitutions EuropeanCommissionDirectorate–GeneralInformationSociety IEEECircuitsandSystemsSociety TableofContents Opening Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 R. vanLeuken,R. Nouta,A. deGraf(DelftUniversityofTechnology, TheNetherlands) RTL Power Modeling Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. . . . . . . . . . . . . . . . . . 3 M. Anton,M. Chinosi,D. Sirtori,R. Zafalon(STMicroelectronics, Italy) Power Models for Semi-autonomous RTL Macros . . . . . . . . . . . . . . . . . . . . . . 14 A. Bogliolo(UniversityofFerrara,Italy) E. Macii,V. Mihailovici,M. Poncino(PolytechnicalUniversityofTorino, Italy) Power Macro-Modelling for Firm-Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 G. Jochens,L. Kruse,E. Schmidt,A. Stammermann,W. ".
catalog extent "xii, 338 p. :".
catalog identifier "3540410686 (softcover : alk. paper)".
catalog isPartOf "Lecture notes in computer science ; 1918".
catalog issued "2000".
catalog issued "2000.".
catalog language "eng".
catalog publisher "Berlin ; New York : Springer,".
catalog subject "621.39/5 21".
catalog subject "Computer science.".
catalog subject "Computer system performance.".
catalog subject "Computer-aided design Congresses.".
catalog subject "Integrated circuits Very large scale integration Design Data processing Congresses.".
catalog subject "Logic design.".
catalog subject "TK7874.75 .P38 2000".
catalog tableOfContents "Cost-Efficient C-Level Design of an MPEG-4 Video Decoder -- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications -- AdiabaticDesign and ArithmeticModules -- Design of Reversible Logic Circuits by Means of Control Gates -- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates -- An Adiabatic Multiplier -- Logarithmic Number System for Low-Power Arithmetic -- Analog-Digital Circuits Modeling -- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits -- PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits -- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits -- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.".
catalog tableOfContents "Opening -- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action -- RTL Power Modeling -- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques -- Power Models for Semi-autonomous RTL Macros -- Power Macro-Modelling for Firm-Macro -- RTL Estimation of Steering Logic Power -- Power Estimation and Optimization -- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers -- Framework for High-Level Power Estimation of Signal Processing Architectures -- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses -- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions -- System-Level Design -- A Holistic Approach to System Level Energy Optimization -- Early Power Estimation for System-on-Chip Designs -- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures -- ".
catalog tableOfContents "Transistor-Level Modeling -- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design -- Impact of Voltage Scaling on Glitch Power Consumption -- Degradation Delay Model Extension to CMOS Gates -- Second Generation Delay Model for Submicron CMOS Process -- Asynchronous Circuit Design -- Semi-modular Latch Chains for Asynchronous Circuit Design -- Asynchronous First-in First-out Queues -- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance -- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder -- Power Efficient Technologies -- Low Power Design Techniques for Contactless Chipcards -- Dynamic Memory Design for Low Data-Retention Power -- Double-Latch Clocking Scheme for Low-Power I.P. Cores -- Design of Multimedia Processing Applications -- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip -- ".
catalog title "Integrated circuit design : power and timing modeling, optimization, and simulation : 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 : proceedings / Dimitrios Soudris, Peter Pirsch, Erich Barke (eds.).".
catalog type "Conference proceedings. fast".
catalog type "text".