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• catalog abstract "We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology.".
• catalog contributor b12406746.
• catalog contributor b12406747.
• catalog contributor b12406748.
• catalog contributor b12406749.
• catalog created "c2001.".
• catalog date "2001".
• catalog date "c2001.".
• catalog dateCopyrighted "c2001.".
• catalog description "A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro / Junji Ogawa and Mark Horowitz -- Software Controlled Reconfigurable On-Chip Memory for High Performance Computing / Hiroshi Nakamura, Masaaki Kondo and Taisuke Boku -- Content-Based Prefetching: Initial Results / Robert Cooksey, Dennis Colarelli and Dirk Grunwald -- Memory System Support for Dynamic Cache Line Assembly / Lixin Zhang, Venkata K. Pingali and Bharat Chandramouli / [and others] -- Adaptively Mapping Code in an Intelligent Memory Architecture / Yan Solihin, Jaejin Lee and Josep Torrellas -- The Characterization of Date Intensive Memory Workloads on Distributed PIM Systems / Richard C. Murphy, Peter M. Kogge and Arun Rodrigues.".
• catalog description "Includes bibliographical references and index.".
• catalog description "We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology.".
• catalog extent "viii, 191 p. :".
• catalog identifier "3540423281 (pbk. : alk. paper)".
• catalog isPartOf "Lecture notes in computer science, 0302-9743 ; 2107".
• catalog issued "2001".
• catalog issued "c2001.".
• catalog language "eng".
• catalog publisher "Berlin ; New York : Springer,".
• catalog subject "005.4/35 21".
• catalog subject "Computer network architectures.".
• catalog subject "Computer science.".
• catalog subject "Logic design.".
• catalog subject "Memory management (Computer science) Congresses.".
• catalog subject "Memory management (Computer science).".
• catalog subject "Operating systems (Computers).".
• catalog subject "QA76.9.M45 I94 2000".
• catalog subject "Systems software Congresses.".
• catalog tableOfContents "A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro / Junji Ogawa and Mark Horowitz -- Software Controlled Reconfigurable On-Chip Memory for High Performance Computing / Hiroshi Nakamura, Masaaki Kondo and Taisuke Boku -- Content-Based Prefetching: Initial Results / Robert Cooksey, Dennis Colarelli and Dirk Grunwald -- Memory System Support for Dynamic Cache Line Assembly / Lixin Zhang, Venkata K. Pingali and Bharat Chandramouli / [and others] -- Adaptively Mapping Code in an Intelligent Memory Architecture / Yan Solihin, Jaejin Lee and Josep Torrellas -- The Characterization of Date Intensive Memory Workloads on Distributed PIM Systems / Richard C. Murphy, Peter M. Kogge and Arun Rodrigues.".
• catalog title "Intelligent memory systems : Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000 : revised papers / Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin (eds.).".
• catalog type "Cambridge (Mass., 2000) swd".
• catalog type "Conference proceedings. fast".
• catalog type "Kongress. swd".
• catalog type "text".