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- catalog contributor b13012679.
- catalog contributor b13012680.
- catalog contributor b13012681.
- catalog created "2003.".
- catalog date "2003".
- catalog date "2003.".
- catalog dateCopyrighted "2003.".
- catalog description "Architectural Challenges for the Next Decade Integrated Platforms / A. Cuomo -- Analysis of High-Speed Logic Families / G. Privitera and F. Pessolano -- Low-Voltage, Double-Edge-Triggered Flip Flop / P. Varma and A. Chakraborty -- A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems / G. Ascia, V. Catania and M. Palesi -- State Encoding for Low-Power FSMs in FPGA / L. Mengibar, L. Entrena, M.G. Lorenz and R. Sanchez-Reillo -- Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies / T. Schoenauer, J. Berthold and C. Heer -- A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates / J.L. Rossello and J. Segura.".
- catalog description "Includes bibliographical references and index.".
- catalog extent "xvii, 631 p. :".
- catalog identifier "3540200746".
- catalog issued "2003".
- catalog issued "2003.".
- catalog language "eng".
- catalog publisher "Berlin ; New York : Springer,".
- catalog subject "621.39/5 22".
- catalog subject "Integrated circuits Very large scale integration Computer-aided design Congresses.".
- catalog subject "TK7874.75 .P38 2003".
- catalog tableOfContents "Architectural Challenges for the Next Decade Integrated Platforms / A. Cuomo -- Analysis of High-Speed Logic Families / G. Privitera and F. Pessolano -- Low-Voltage, Double-Edge-Triggered Flip Flop / P. Varma and A. Chakraborty -- A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems / G. Ascia, V. Catania and M. Palesi -- State Encoding for Low-Power FSMs in FPGA / L. Mengibar, L. Entrena, M.G. Lorenz and R. Sanchez-Reillo -- Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies / T. Schoenauer, J. Berthold and C. Heer -- A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates / J.L. Rossello and J. Segura.".
- catalog title "Integrated circuit and system design : power and timing modeling, optimization and simulation : 13th International Workshop, PATMOS 2002, Torino, Italy, September 10-12, 2003 : proceedings / Jorge Juan Chico, Enrico Macii, (Eds.)".
- catalog type "Conference proceedings. fast".
- catalog type "text".