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- 2003062044 contributor B9553373.
- 2003062044 contributor B9553374.
- 2003062044 created "2003.".
- 2003062044 date "2003".
- 2003062044 date "2003.".
- 2003062044 dateCopyrighted "2003.".
- 2003062044 description "Includes bibliographical references and index.".
- 2003062044 extent "xiv, 216 p. :".
- 2003062044 identifier "1402076525 (alk. paper)".
- 2003062044 identifier 2003062044-d.html.
- 2003062044 identifier 2003062044-t.html.
- 2003062044 isPartOf "Frontiers in electronic testing ; 25".
- 2003062044 issued "2003".
- 2003062044 issued "2003.".
- 2003062044 language "eng".
- 2003062044 publisher "Boston : Kluwer Academic Publishers,".
- 2003062044 subject "621.39/5 22".
- 2003062044 subject "Error analysis (Mathematics)".
- 2003062044 subject "Integrated circuits Verification.".
- 2003062044 subject "Integrated circuits Very large scale integration Computer-aided design.".
- 2003062044 subject "TK7874.75 .R33 2003".
- 2003062044 title "Verification by error modeling : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.".
- 2003062044 type "text".