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- 2007271541 contributor B10815815.
- 2007271541 contributor B10815816.
- 2007271541 created "c2006.".
- 2007271541 date "2006".
- 2007271541 date "c2006.".
- 2007271541 dateCopyrighted "c2006.".
- 2007271541 description "Includes bibliographical references.".
- 2007271541 extent "xvii, 267 p. :".
- 2007271541 identifier "1860945899 (hb)".
- 2007271541 identifier "9781860945892 (hb)".
- 2007271541 identifier 2007271541.html.
- 2007271541 issued "2006".
- 2007271541 issued "c2006.".
- 2007271541 language "eng".
- 2007271541 publisher "London : Imperial College Press,".
- 2007271541 subject "003.3 22".
- 2007271541 subject "Integrated circuits Very large scale integration.".
- 2007271541 subject "Metal oxide semiconductors, Complementary.".
- 2007271541 subject "TK7868.T5 B45 2006".
- 2007271541 subject "Timing circuits.".
- 2007271541 title "Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia.".
- 2007271541 type "text".