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- 2007929117 alternative "Closing the power gap between ASIC and custom".
- 2007929117 contributor B11060481.
- 2007929117 contributor B11060482.
- 2007929117 created "c2007.".
- 2007929117 date "2007".
- 2007929117 date "c2007.".
- 2007929117 dateCopyrighted "c2007.".
- 2007929117 description "Ch. 1. Introduction -- Ch. 2. Overview of the factors affecting the power consumption -- Ch. 3. Pipelining to reduce the power -- Ch. 4. Voltage sealing -- Ch. 5. Methodology to optimize energy of computation for SOCs -- Ch. 6. Linear programming for gate sizing -- Ch. 7. Linear programming for multi-Vth and multi-Vdd assignment -- Ch. 8. Power optimization using multiple supply voltages -- Ch. 9. Placement for power optimization -- Ch. 10. Power gating design automation -- Ch. 11. Verification for multiple supply voltage designs -- Ch. 12. Winning the power struggle in an uncertain era -- Ch. 13. Pushing ASIC performance in a power envelope -- Ch. 14. Low power ARM 1136JF-S design.".
- 2007929117 description "Includes bibliographical references and index.".
- 2007929117 extent "xii, 384 p. :".
- 2007929117 identifier "0387257632 (hbk.)".
- 2007929117 identifier "1441938338".
- 2007929117 identifier "9780387257631 (hbk.)".
- 2007929117 identifier "9781441938336".
- 2007929117 identifier 2007929117-d.html.
- 2007929117 identifier 2007929117-t.html.
- 2007929117 issued "2007".
- 2007929117 issued "c2007.".
- 2007929117 language "eng".
- 2007929117 publisher "New York : Springer Science+Business Media,".
- 2007929117 subject "621.3815 22".
- 2007929117 subject "Application-specific integrated circuits.".
- 2007929117 subject "Basse tension. ram".
- 2007929117 subject "Circuits imprimés Conception et construction Informatique. ram".
- 2007929117 subject "Circuits intégrés. ram".
- 2007929117 subject "Low voltage integrated circuits Design.".
- 2007929117 subject "TK7874.66 .C49 2007".
- 2007929117 subject "sujet. ram".
- 2007929117 tableOfContents "Ch. 1. Introduction -- Ch. 2. Overview of the factors affecting the power consumption -- Ch. 3. Pipelining to reduce the power -- Ch. 4. Voltage sealing -- Ch. 5. Methodology to optimize energy of computation for SOCs -- Ch. 6. Linear programming for gate sizing -- Ch. 7. Linear programming for multi-Vth and multi-Vdd assignment -- Ch. 8. Power optimization using multiple supply voltages -- Ch. 9. Placement for power optimization -- Ch. 10. Power gating design automation -- Ch. 11. Verification for multiple supply voltage designs -- Ch. 12. Winning the power struggle in an uncertain era -- Ch. 13. Pushing ASIC performance in a power envelope -- Ch. 14. Low power ARM 1136JF-S design.".
- 2007929117 title "Closing the power gap between ASIC & custom : tools and techniques for low power design / David Chinnery, Kurt Keutzer.".
- 2007929117 title "Closing the power gap between ASIC and custom".
- 2007929117 type "text".