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- 2008045600 contributor B11125998.
- 2008045600 contributor B11125999.
- 2008045600 created "c2009.".
- 2008045600 date "2009".
- 2008045600 date "c2009.".
- 2008045600 dateCopyrighted "c2009.".
- 2008045600 description "Includes bibliographical references and index.".
- 2008045600 description "Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.".
- 2008045600 extent "xiii, 249 p. :".
- 2008045600 identifier "0470824077 (cloth)".
- 2008045600 identifier "9780470824078 (cloth)".
- 2008045600 issued "2009".
- 2008045600 issued "c2009.".
- 2008045600 language "eng".
- 2008045600 publisher "Singapore ; Hoboken, NJ : Wiley ; [Piscataway, NJ] : IEEE Press,".
- 2008045600 subject "621.39/5 22".
- 2008045600 subject "Metal oxide semiconductors, Complementary Defects.".
- 2008045600 subject "Metal oxide semiconductors, Complementary Reliability.".
- 2008045600 subject "TK7871.99.M44 K47 2009".
- 2008045600 subject "Transients (Electricity)".
- 2008045600 tableOfContents "Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.".
- 2008045600 title "Transient-induced latchup in CMOS integrated circuits / Ming-Dou Ker and Sheng-Fu Hsu.".
- 2008045600 type "text".