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- 2008050653 contributor B11132182.
- 2008050653 created "2009.".
- 2008050653 date "2009".
- 2008050653 date "2009.".
- 2008050653 dateCopyrighted "2009.".
- 2008050653 description "Includes bibliographical references and index.".
- 2008050653 description "Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva.".
- 2008050653 extent "xi, 276 p. :".
- 2008050653 identifier "0521859727 (hardback)".
- 2008050653 identifier "9780521859721 (hardback)".
- 2008050653 issued "2009".
- 2008050653 issued "2009.".
- 2008050653 language "eng".
- 2008050653 publisher "Cambridge, UK ; New York : Cambridge University Press,".
- 2008050653 subject "621.3815/48 22".
- 2008050653 subject "Integrated circuits Verification.".
- 2008050653 subject "TK7874.58 .P73 2009".
- 2008050653 tableOfContents "Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva.".
- 2008050653 title "Practical design verification / edited by Dhiraj K. Pradhan, Ian G. Harris.".
- 2008050653 type "text".