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- 2009419424 contributor B11590872.
- 2009419424 created "c2010.".
- 2009419424 date "2010".
- 2009419424 date "c2010.".
- 2009419424 dateCopyrighted "c2010.".
- 2009419424 description "Includes bibliographical references (p. [565]-566) and index.".
- 2009419424 description "Introduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A: Tool and setup scripts -- Appendix B: Scripts to drive the tools -- Appendix C: Technology and cell libraries.".
- 2009419424 extent "xvi, 571 p. :".
- 2009419424 identifier "0321547993".
- 2009419424 identifier "9780321547996".
- 2009419424 issued "2010".
- 2009419424 issued "c2010.".
- 2009419424 language "eng".
- 2009419424 publisher "Boston : Addison-Wesley,".
- 2009419424 subject "621.3815 22".
- 2009419424 subject "Entwurfsautomation. swd".
- 2009419424 subject "Integrated circuits Very large scale integration Computer-aided design.".
- 2009419424 subject "TK7874.75 .B78 2010".
- 2009419424 subject "VLSI. swd".
- 2009419424 tableOfContents "Introduction -- Cadence DFII and ICFB -- Composer schematic capture -- Verilog simulation -- Virtuoso layout editor -- Standard cell design template -- Spectre analog simulator -- Cell characterization -- Verilog synthesis -- Abstract generation -- SOC encounter place and route -- Chip assembly -- Design example -- Appendix A: Tool and setup scripts -- Appendix B: Scripts to drive the tools -- Appendix C: Technology and cell libraries.".
- 2009419424 title "Digital VLSI chip design with Cadence and Synopsys CAD tools / Erik Brunvand.".
- 2009419424 type "text".