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- 2010934904 contributor B12094199.
- 2010934904 created "2010.".
- 2010934904 date "2010".
- 2010934904 date "2010.".
- 2010934904 dateCopyrighted "2010.".
- 2010934904 description "Includes bibliographical references and index.".
- 2010934904 description "Pt. 1. Opening -- pt. 2. Assertions -- pt. 3. Checkers and assertion libraries.".
- 2010934904 extent "xvi, 544 p. ;".
- 2010934904 identifier "1441965998 (hbk. : alk. paper)".
- 2010934904 identifier "9781441965998 (hbk. : alk. paper)".
- 2010934904 identifier "9781441966001 (e-ISBN)".
- 2010934904 issued "2010".
- 2010934904 issued "2010.".
- 2010934904 language "eng".
- 2010934904 publisher "New York ; London : Springer,".
- 2010934904 subject "621.381548 22".
- 2010934904 subject "Integrated circuits Verification Data processing.".
- 2010934904 subject "TK7874.58 .P69 2010".
- 2010934904 subject "Verilog (Computer hardware description language)".
- 2010934904 tableOfContents "Pt. 1. Opening -- pt. 2. Assertions -- pt. 3. Checkers and assertion libraries.".
- 2010934904 title "The power of assertions in SystemVerilog / Eduard Cerny ... [et al.].".
- 2010934904 type "text".