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- aggregation classification "B2".
- aggregation creator B1032342.
- aggregation creator B1032343.
- aggregation creator person.
- aggregation date "2010".
- aggregation format "application/pdf".
- aggregation hasFormat 1153474.bibtex.
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- aggregation isPartOf urn:isbn:9781441963444.
- aggregation language "eng".
- aggregation publisher "Springer".
- aggregation rights "I have transferred the copyright for this publication to the publisher".
- aggregation subject "Technology and Engineering".
- aggregation title "Coarse-grained reconfigurable array architectures".
- aggregation abstract "Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.".
- aggregation authorList BK1449661.
- aggregation endPage "484".
- aggregation startPage "449".
- aggregation aggregates 1153493.
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- aggregation similarTo 978-1-4419-6345-1_17.
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